Interrupt Communication on the SegBus platform

Abstract

In this study, we discuss communication aspects concerning a segmented bus platform. The segmented bus architecture provides certain performance improvements compared to the traditional bus systems, while employing a much simpler communication structure and algorithm than those thought for networks-on-chip. Our implementation strategy targets an FPGA technology and considers multiple clock domains. By means of interrupt-like procedures, we obtain both improvements in performance and accurate throughput characterization.