First Pass MM-Wave Circuit Design in 65nm Digital CMOS

Abstract

A 60 GHz gain block is designed in a 65 nm digital CMOS 1P9M process using only digital CMOS models and a reduced metallization stack-up height to support redistribution layer routing for flip-chip designs. The design methodology utilizes current density, distributed, and lumped modeling to predict the measured center frequency of the gain block less than 1% from the simulated values. At 1 V and 5.3 mA, measured S ₁₂ , Sn, S ₁₁ , S ₂₂ , NF, and IP _1dB are 3dB, <-20dB, <-10dB, <-15 dB, 7.7 dB and -6 dBm respectively, across 57-64 GHz. Measurements at 2 V are also presented.