RF-analog circuit design in scaled SoC

Abstract

Downscaling of process technology increases the development cost of RFCMOS SoC. Therefore, designers have to minimize the number of respins, and have to try to obtain higher yield. RFCMOS SoC consists of RF-analog, mixed-signal, logic and memory circuits. In order to realize a small number of respins number and higher yield, key issues are robust design methodology of RF-analog circuits, and full-chip verification. This paper describes practical techniques corresponding to those issues.