ATM network interface architectures for low latency

Abstract

There are many important factors to consider when designing a network interface for an ATM network, and different applications have different demands. This paper addresses the problem of making an ATM interface with the focus on very low message latency, e.g., for shared memory multiprocessors on top of a network of workstations, and yet making it general enough to be a cost effective solution. Different approaches to the interface are evaluated and an architecture where critical functions are distributed and performed in dedicated hardware, integrated with, or very close to, the processors, are proposed.