VLSI implementations of stereo matching using Dynamic Programming

Abstract

Dynamic Programming (DP)-based stereo matching consists of three major parts: matching cost computation (M.C.C.), minimum cost accumulation (M.C.A.), and disparity optimization (D.O.). This paper presents two architectures of implementations: array-based and memory-based. The array-based implementation is a systolic-like design consisting of regularly connected processing elements (PEs). The memory-based design replaces most of the PEs by memory units in order to reduce area cost. Both architectures adopt the concept of double buffer designs in order to process contiguous images. Experimental results show that the proposed design can achieve real-time processing speed at reasonable area cost.