JOURNAL ARTICLE

Dispatching in an integrated circuit wafer fabrication line

Abstract

Wafer Fabrication has been described as the most complicated manufacturing environment existing today. This paper describes a method used to dispatch lots in one of AT&T's Wafer Fabrication Clean Rooms. The objective is to minimize idle time on important facilities in the clean room. For each lot in the clean room, the method indicates the slack time the lot can incur before it is needed at the next important facility group in its route. The slack time is the amount of time the lot can be delayed in queue with the implication that a lot with a smaller slack time needs to be processed more urgently than a lot with a larger slack time.

Keywords:
Wafer fabrication Wafer Queue Idle Fabrication Computer science Cleanroom Line (geometry) Embedded system Automotive engineering Reliability engineering Engineering Electrical engineering Operating system Computer network Materials science

Metrics

12
Cited By
2.10
FWCI (Field Weighted Citation Impact)
5
Refs
0.88
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Scheduling and Optimization Algorithms
Physical Sciences →  Engineering →  Industrial and Manufacturing Engineering
Advanced Manufacturing and Logistics Optimization
Physical Sciences →  Engineering →  Industrial and Manufacturing Engineering
Manufacturing Process and Optimization
Physical Sciences →  Engineering →  Industrial and Manufacturing Engineering

Related Documents

JOURNAL ARTICLE

Dispatching In An Integrated Circuit Wafer Fabrication Line

P.K. John

Journal:   1989 Winter Simulation Conference Proceedings Year: 2005 Pages: 918-921
JOURNAL ARTICLE

An integrated dispatching rule with on‐line rework consideration in wafer fabrication

Shu-Yen HsuD. Y. ShaY.H. Chang

Journal:   Journal of Manufacturing Technology Management Year: 2009 Vol: 20 (8)Pages: 1166-1182
JOURNAL ARTICLE

Integrated lot sizing and dispatching in wafer fabrication

M. ChenSubhash C. SarinA.H. Peake

Journal:   Production Planning & Control Year: 2010 Vol: 21 (5)Pages: 485-495
JOURNAL ARTICLE

Dispatching heuristic for wafer fabrication

Loo Hy LeeLoon Ching TangSoon Chee Chan

Journal:   Proceeding of the 2001 Winter Simulation Conference (Cat. No.01CH37304) Year: 2002 Vol: 2 Pages: 1215-1219
JOURNAL ARTICLE

Dispatching heuristic for wafer fabrication

Loo Hay LeeLoon Ching TangSoon Chee Chan

Journal:   Winter Simulation Conference Year: 2001 Vol: 2 Pages: 1215-1219
© 2026 ScienceGate Book Chapters — All rights reserved.