Mechanical characterization of next generation eWLB (embedded wafer level BGA) packaging

Abstract

Integrated Circuits fabricated on silicon are assembled in different forms of electronic packages and are used extensively in electronic products such as personal, portable, healthcare, entertainment, industrial, automotive, environmental and security systems. Current and future demand for these electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in component level and board level reliability of next generation eWLB technologies including multi-RDL, thin eWLB, extra large eWLB with multi-chip. Standard JEDEC tests were carried out to investigate component level reliability and both failure analysis was performed to investigate potential structural defects. Daisychain eWLBs were assembled with different package size and different configuration as like thin or multi-RDL or multi-die. Test vehicles were also tested for drop and TCoB (Temperature on Board) reliability in industry standard test conditions. Next generation test vehicles passed both drop and TCoB tests. There was more than 50% improvement of characteristic lifetime with thinned eWLB in TCoB test because of its enhanced flexibility of package. This paper also presents study of package warpage behavior with temperature profile which is important for understanding of mechanical behavior of next generation 3D eWLBs.