Model Based Verification of SystemC Designs

Abstract

Recent advancement in system-on-chip design leads to the promotion of system level languages such as SystemC. This latter enables rapid prototyping and fast simulation in comparison to the classical register transfer level (RTL) based approach. Intuitively, from a verification point of view, faster simulation induces better coverage results. In this paper, we propose a methodology to verify SystemC designs. We propose an automatic generation procedure of the system's finite state machine (FSM) from SystemC. The generated FSM is then used to produce test suites allowing functional testing of SystemC designs. Furthermore, the same FSM is used to perform conformance testing to validate lower abstraction levels of the design (e.g., RTL). We illustrate the feasibility and efficiency of our approach on a PCI bus standard