Super-integrated bipolar memory device for high-density, low-power storage

Abstract

A novel bipolar memory device for high-density, low power read/write storages has been developed, fabricated and analyzed. It has been operated at a standby power of 100 nanowatts and can be conveniently switched to currents larger by orders of magnitude to speed up the read and write operation. The cell size of 4 mil ² achieved by conventional processing with a 3µ epitaxial layer thickness and a minimum metal line width of 0.25 mils (spacing 0.15 mil) allows at least 2000 bits/chip. Despite this high density an access/cycle time of about 60/150ns has been projected from array simulation measurements on single devices. In contrast to other approaches in this bit density range, this statically stable device does not require any refresh operation.