VLSI designs for redundant binary-coded decimal addition

Abstract

A binary-coded decimal system provides rapid binary-decimal conversion. However, BCD arithmetic operations are often slow and require complex hardware. One can eliminate the need for carry propagation and thus improve performance of BCD operations by using a redundant binary-coded decimal (RBCD) system. The VLSI design of an RBCD adder is introduced. The design consists of two small PLAs and two four-bit binary adders for one digit of the RBCD adder. The addition delay is constant for n-digit RBCD addition (no carry propagation delay). The VLSI time and space complexities of the design, as well as its layout are presented, showing the regularity of the structures. Two simple algorithms and the corresponding hardware designs for conversion between RBCD and BCD are presented.< >