Tree-based transistor topology extraction algorithm for library-free logic synthesis

Abstract

Library-free logic synthesis is an innovative approach that provides a fully customized design performance while avoiding the huge cost of developing and maintaining the extensive cell libraries. Its strength is coming from the use of a virtual library based on on-the-fly cell generation. However, the flexibility of the virtual library makes it impossible to exploit the existing methodologies that are based on the library pre-characterization. New models have to be developed to predict the performance of the potential gate based on the topology of the transistor circuit. The authors have designed an algorithm that extracts the transistor topology of the CMOS complex gate from the Boolean network. The proposed algorithm is based on the linear-matrix layout style and performance-driven transistor placement. It plays a significant role in the topology-based performance estimation model.