Fault-Tolerant Bit-Parallel Multiplier for Polynomial Basis of GF(2m)

Abstract

In this paper, we present novel fault-tolerant architecture for bit-parallel polynomial basis multiplier over GF(2m) which can correct the erroneous outputs using linear code. We have designed a parity prediction circuit based on the code generator polynomial that leads lower space overhead. For bit-parallel architectures, the space overhead is about 11%. Moreover, there is only marginal time overhead due to incorporation of error-correction capability that amounts to 3.5% in case of the bit-parallel multiplier. Unlike the existing concurrent error correction (CEC) multipliers or triple modular redundancy (TMR) techniques for single error correction, the proposed architectures have multiple error-correcting capabilities.