Design of 32-bit TX2 microprocessor based on TRON specifications

Abstract

The TX2 processor is the second implementation in the Toshiba TLCS90000/TX series of 32-b microprocessors based on the TRON specification. The TX2 micro-architecture defines five functional units which implement a four-stage pipeline. Basic instructions with register-register operation are executed in a single cycle with a single step of microcode. The TX2 has a performance of 25 MIPS and executes about 20,000 dhrystones/second at 25 MHz with zero wait external bus cycle. Design of the TX2 is based on full custom LSI design methodology. To increase the operating frequency of the CISC microprocessor TX2, timing design based on static path delay analysis was performed. As a result, high speed processing has been achieved.