A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS

Abstract

Transistors in aggressively scaled CMOS technologies have f _T greater than 150 GHz, which exceeds requirements for most existing commercial applications below 10 GHz. Excess transistor performance can be traded-off for cost by designing out inductors. This paper presents a prototype which exploits the speed of transistors to design highly integrated broadband receiver front-ends. The inductor-less prototype operates from 2 to 5.8 GHz and dissipates 85 mW at 5 GHz while occupying 0.2 mm ² active area. It provides 44 dB of gain, 3.4 dB double side band noise figure, 21 dBm in-band IIP3 in the highest gain mode and 15 dB input matching.