A two-way graph partitioning using a heuristic procedure

Abstract

Partitioning a circuit is an important task in many phases of very large scale integrated (VLSI) design, ranging from layout to testing and hardware simulation. This problem is a variant of the more general graph partitioning problem. It is known that there is no polynomial time algorithm to obtain an optimal partition. A number of heuristic procedures have been proposed to obtain a sub-optimal solution. We discuss an implementation of a heuristic procedure for 2-way partitioning of circuit netlist. We use an iterative improvement method in which an initial partition is generated and then it is improved to get the final solution. The circuit partitioning procedure incorporates heuristics to partition the functional modules into two groups A and B such that the number of nets between the groups is as small as possible and the area of the modules in each group is nearly equal. Since the two conditions are contradictory in nature, we use a trade-off function for the partition A and B. We discuss the nature of the function, implementation of the partition procedure and the results.