A RISC architecture to explore HW/SW parallelism in HW/SW codesign

Abstract

The paper describes some modifications on the architecture of embedded RISC-like processors to better explore HW/SW (hardware/software) parallelism in a HW/SW co-design environment. It is shown that the inclusion of an instruction memory allows parallel execution of the application SW and eventual dedicated HW. Positive results are shown for two different RISC microprocessors. The paper also reports experimental results, particularly the proposed modifications applied to an induction motor control algorithm.