Energy-Aware Cache Coherence Protocol for Chip-Multiprocessors

Abstract

Chip-multiprocessors (CMs) are gaining popularity for future microprocessors to be used in high-end systems (e.g., server machines) as well as in the low-power systems (e.g., mobile devices, laptops). The CM system consists of several processors cores connected to their respective L1 caches via a bus, and a common L2 cache. The design of a cache coherence protocol in CM presents unique challenges when the power consumption is as important an issue as the overall performance. This paper presents a new energy-aware cache coherence protocol for CMs that minimizes the snoop traffic. The paper shows that a tradeoff exists between the cache performance and the power saving in the cache system, in general. The system uses L1 cache to store only the instructions for the related processor while L2 cache stores both the instructions and the data. The paper presents an analytical model for power estimation and average memory access time. Several results under various parameter changes are presented and trade-offs are highlighted. The results of the proposed protocol are also compared with some existing snoopy cache coherence protocols