Multi-pipeline Architecture for Face Recognition on FPGA

Abstract

In this paper, a new multi-pipeline architecture is proposed for face recognition system on FPGA. The proposed structure consists of four main units: Multi-pipeline control unit (MPCU), process element unit (PEU), region summing unit (RSU), and recognition indexing unit (RIU). Four recognition techniques: Principal component analysis (PCA), modular PCA (MPCA), Weight MPCA (WMPCA), and Wavelet based techniques are adopted to evaluate the efficiency of the proposed architecture using several standard face databases. The experimental results show that the proposed architecture helps minimizing processing time through its multi-pipeline processes while still maintains high recognition rate. Moreover, the design has encouraged the reduction in hardware resources by utilizing the proposed reusable modules.