Jason C. ChenChun-Fu ShenShao‐Yi Chien
A 345Mpixels/s coarse-grained reconfigurable image stream processor (CRISP) is proposed and implemented with 5 mm2 area in 0.18 μ m CMOS technology for the image pipelines of digital still cameras and video camcoders. The novel CRISP architecture with scalable reconfigurable stage processing elements and reconfigurable interconnection could achieve high processing speed at low cost, while satisfying the flexibility and performance requirements of high-end image preprocessing for 10M-pixel scale still cameras and 1920×1080 camcorders. CRISP can execute image pipelines 83 times faster than the state-of-the-art digital signal processor with only about one-tenth die size.
Teng-Yuan ChengTsung-Huang ChenC. Chen JasonShao‐Yi Chien
Wei-Kai ChanYu-Hsiang TsengYu‐Sheng LinShao‐Yi Chien
J.C. ChenChun-Fu ShenShao‐Yi Chien