Abstract

Our two-chip, real time, MPEG-2, simple-profile-at-main-level encoder supports NTSC 4:2:0 video signals with only three external memories. We have developed a compact encoder chip set. The key features of this chip set are a low encoding delay based on a simple profile at main level; wide-range motion estimation, which it performs using a hierarchical search; a flexible, macroblock level pipeline architecture based on RISC CPUs; and three small peripherals with no glue logic: a VRAM, synchronous DRAM, and FIFO DRAM.

Keywords:
Computer science Macroblock Encoder Computer hardware NTSC FIFO (computing and electronics) Dram Embedded system Pipeline (software) Motion estimation Chip MPEG-2 Encoding (memory) Real-time computing High-definition television Decoding methods Artificial intelligence Algorithm

Metrics

23
Cited By
4.31
FWCI (Field Weighted Citation Impact)
10
Refs
0.95
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Video Coding and Compression Technologies
Physical Sciences →  Computer Science →  Signal Processing
Advanced Data Compression Techniques
Physical Sciences →  Computer Science →  Computer Vision and Pattern Recognition
Error Correcting Code Techniques
Physical Sciences →  Computer Science →  Computer Networks and Communications
© 2026 ScienceGate Book Chapters — All rights reserved.