Efficient Use of Processing Cores on Heterogeneous Multicore Architecture

Abstract

One of the major challenges of multicore architectures is not only to aim toward high performance but also to efficiently harness the computing power of these systems. This is especially true for embedded systems where problems of energy and silicon efficiencies are critical. Multicore architectures provide significant gains for explicitly multi-threaded or dataflow applications. However, single-task applications commonly found in embedded systems do not fit well with current multicore architectures. To maximize performance and efficiency of the chip, communication and allocation-synchronization problems need to be addressed in concert with a coherent and carefully crafted approach of the programming interface. This paper focuses on allocation-synchronization problems and the programming interface of these architectures. The proposed mechanism is based on an intermediate level of parallelism and provides a solution for allocating and synchronizing processing cores with an easy to use instruction set architecture. This mechanism avoids global synchronization of cores when interruptions or exceptions occur on the main processor. This increases core utilizations among all applications executed on the chip and thus, chip efficiency. A preliminary evaluation has shown significant improvements in terms of performance, energy and silicon efficiencies of the chip.