Implementation of Neural Network Back Propagation Training Algorithm on FPGA

Abstract

This work presents the implementation of trainable Artificial Neural Network (ANN) chip, which can be trained to implement certain functions. Usually training of neural networks is done off-line using software tools in the computer system. The neural networks trained off-line are fixed and lack the flexibility of getting trained during usage. In order to overcome this disadvantage, training algorithm can implemented on-chip with the neural network. In this work back propagation algorithm is implemented in its gradient descent form, to train the neural network to function as basic digital gates and also for image compression. The working of back propagation algorithm to train ANN for basic gates and image compression is verified with intensive MATLAB simulations. In order to implement the hardware, verilog coding is done for ANN and training algorithm. The functionality of the verilog RTL is verified by simulations using ModelSim XE III 6.2c simulator tool. The verilog code is synthesized using Xilinx ISE 10.1 tool to get the netlist of ANN and training algorithm. Finally the netlist was mapped to FPGA and the hardware functionality was verified using Xilinx Chipscope Pro Analyzer 10.1 tool. Thus the concept of neural network chip that is trainable on-line is successfully implemented.