Shunt-peaking in MCML memory element design in 0.18μm CMOS technology

Abstract

This paper proposes a new active shunt-peaked realization for MOS Current Mode Logic (MCML) based memory element. The circuit proposes the use of active inductors in shunt-peaking of MCML memory element. The technique of shunt-peaking offers a way of enhancing the performance of gates at high speed of operations. The benefit of the proposed circuit is verified by designing and simulating various MCML based memory elements with resistive, PMOS, feedback and active inductor load. An overall performance evaluation in terms of setup time, hold time and propagation delay from clock-to-Q has been done in PSPICE using 0.18μm TSMC CMOS technology parameters. For a power supply of 3.3 V and clock frequency of 1 GHz, the simulation results show an improvement of 13 to 25 percent in the values of delay parameters for active shunt-peaked memory element in comparison to other existing MCML based designs.