Comparison of CMOS and BiCMOS optical receiver SoCs

Abstract

Currently two very interesting trends in design of optical receivers can be observed. The first is to realize optical receivers in deep-sub-μm CMOS technology and to integrate them in analog-digital systems-on-a-chip (SoC). The second even much more innovative trend is to integrate voltage-up-converters (VUCs) in optoelectronic integrated circuits (OEICs) to increase the bandwidth and data rate, whereby only the chip voltage supply is necessary. The properties of deep-sub-µm CMOS optical receivers and of sub-μm OEICs with respect to current consumption, noise, and chip area will be compared. For both trends a new design each and measured results will be presented. The first example is a burst-mode receiver in digital 0.18μm CMOS technology with sensitivities better than -28 dBm and -22 dBm at data rates of 622Mb/s and 1.25Gb/s, respectively, for a bit error rate of 10-10 each. These values compare to sensitivities of -24.5 dBm and -24.1 dBm, respectively, of a 0.6μm BiCMOS OEIC. For implementation of the burst-mode receiver in an analog-digital SoC, a differential circuit is chosen. Another example is an OEIC in 0.6μm BiCMOS technology with an integrated VUC, which generates a bias voltage of 16V for the integrated photodiode from the chip supply voltage of 5V. Due to the VUC, the data rate for the given technology is increased from 50Mb/s to 1.5Gb/s. The dependence of the receiver sensitivity and of the maximum photocurrent on the VUC clock-frequency will be shown. The VUC-OEIC represents a complete SoC consisting of sensor, analog and digital part. Aspects of substrate noise coupling from the digital part into the photodiode and amplifier are discussed.