FPGA based implementation of parallel ECC processor

Abstract

In recent years many hardware designs of elliptic curve cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field programmable Gate Arrays (FPGA), the major issue concerned the ability of embedding this strategic and strong algorithm in a very few hardware, we propose a scalable word based crypto processor that performs modular multiplication based on modified Montgomery algorithm for finite field GF(P) and GF(2m). The general trend of the hardware implementation of elliptic curve cryptography is to increase throughput by designing a variety of algorithms for the KP operation, by optimizing the architectures of finite field basic operation, and by selecting the most appropriate coordinate system point addition and doubling leave few possibilities for parallelism when considering a single KP operation. It is however possible to explore the design space of an elliptic curve crypto processor sharing the field operators among the computation of some different kP operation. In this paper the obtained parallelism scheme has been evaluated referring to an effective VLSI technology.