<title>Bit synchronization in multigigabit receivers</title>

Abstract

In this paper we report the design and implementation of bit synchronizers for multigigabit transmission systems. We present the main features of dielectric resonators (DRs) and considerations to take into account when using them as filters for clock recovery circuits. We address the problem of using balanced and unbalanced nonlinear circuits (NLs) for which we perform a theoretical analysis of the full-wave and truncated squarer non-linearities. Finally we describe the design of a prototype for a 10 Gbit/s system and report measurements obtained with it.