Low-latency bit-parallel systolic multiplier

Kiamal Pekmestzi; C. Caraiscos

doi:10.1049/el:19930247

ScienceGate Book Chapters

JOURNAL ARTICLE

Low-latency bit-parallel systolic multiplier

Kiamal Pekmestzi C. Caraiscos

Year: 1993 Journal: Electronics Letters Vol: 29 (4)Pages: 367-369 Publisher: Institution of Engineering and Technology

DOI: 10.1049/el:19930247

Get Full-Text PDF Get Analytical Report

Abstract

A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.

Keywords:

Adder Multiplier (economics) Latency (audio) Computer science Systolic array Arithmetic Bit (key) Parallel computing Very-large-scale integration Mathematics Embedded system Telecommunications Computer network

Metrics

Cited By

0.92

FWCI (Field Weighted Citation Impact)

Refs

0.76

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Topics

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Quantum-Dot Cellular Automata

Physical Sciences → Computer Science → Computational Theory and Mathematics

Quantum Computing Algorithms and Architecture

Physical Sciences → Computer Science → Artificial Intelligence

Low-latency bit-parallel systolic multiplier

Abstract

Metrics

Topics

Related Documents

Low-latency bit-parallel systolic VLSI implementation of FIR digital filters

Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials

Reed-Solomon Decoder Architecture Using Bit-Parallel Systolic Multiplier

Low complexity design of bit parallel polynomial basis systolic multiplier using irreducible polynomials

A Systolic Bit-Parallel Multiplier with Flexible Latency and Complexity over GF(2m) Using Polynomial Basis