<title>Efficient VLSI architecture for block-matching motion estimation</title>

Abstract

Motion estimation reduces temporal redundancies in a video sequence, and becomes the most demanding part in video source encoders where motion compensated transform coding method is used. Block matching algorithm needs a large amount of computational load, but its regular data flow structure is good to implement with various parallel processing architectures. In this paper, we present a new VLSI architecture for block matching motion estimation in video encoding systems. The proposed architecture is based on linear systolic arrays. The proposed architecture has (1) fully pipelining operation which achieves 100 percent efficiency of processing elements, (2) efficient data input scheme for high input-rate video encoding systems, (3) glueless interfaces for easy extension of search range by cascaded multiple chip connections, (4) very regular and modular structure which is good to ASIC implementation.