Low-power low-noise CMOS chopper amplifier

Abstract

Chopping technique is an efficient approach to decrease the low-frequency offset and 1/f noise of amplifiers. In this paper, a low-power low-noise CMOS chopper amplifier is designed. This chopper amplifier is composed of a two-stage amplifier. The high output impedance of the first stage and the equivalent Miller capacitance of the second stage amplifier constitute together a low pass filter to filter out the modulation noise, so the chopper amplifier need not the post low-pass filter, which can reduce the power consumption. The circuit of the presented chopper amplifier is designed and simulated with TSMC 0.18μm CMOS process and a 1.8V supply. Simulation results show that the equivalent input noise is 39nV/√Hz at 100 Hz and the power consumption is 117μW.