A 65nm CMOS dual-band RF receiver front-end for DVB-H

Abstract

A dual-band RF receiver front-end for DVB-H is presented in this paper. It includes two sets of single-ended input LNAs, respectively followed by a double-balanced current-driven passive mixer with a low impedance load. The receiver front-end is implemented in a 1P6M 65 nm CMOS process and occupies a total chip area of 2.17 mm ² . It exhibits a conversion gain of 36.5 dB, an IIP3 of −13.1 dBm, an IIP2 of 37 dBm, and a NF of 3.9–4.2 dB in the UHF band, while exhibiting a conversion gain of 37 dB, an IIP3 of −12 dBm, an IIP2 of better than 33 dBm, and a NF of 5.5 dB in the L-band. The total chip draws 32–34mA from a 1.2 V supply voltage.