JOURNAL ARTICLE

Lower bounds for resolution and cutting plane proofs and monotone computations

Pavel Pudlák

Year: 1997 Journal:   Journal of Symbolic Logic Vol: 62 (3)Pages: 981-998   Publisher: Cambridge University Press

Abstract

Abstract We prove an exponential lower bound on the length of cutting plane proofs. The proof uses an extension of a lower bound for monotone circuits to circuits which compute with real numbers and use nondecreasing functions as gates. The latter result is of independent interest, since, in particular, it implies an exponential lower bound for some arithmetic circuits.

Keywords:
Mathematical proof Monotone polygon Mathematics Upper and lower bounds Exponential function Resolution (logic) Electronic circuit Discrete mathematics Computation Proof complexity Extension (predicate logic) Plane (geometry) Combinatorics Algorithm Computer science Mathematical analysis Geometry Physics

Metrics

413
Cited By
10.04
FWCI (Field Weighted Citation Impact)
31
Refs
0.99
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Numerical Methods and Algorithms
Physical Sciences →  Computer Science →  Computational Theory and Mathematics
Formal Methods in Verification
Physical Sciences →  Computer Science →  Computational Theory and Mathematics
Complexity and Algorithms in Graphs
Physical Sciences →  Computer Science →  Computational Theory and Mathematics

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