Testing power-analysis attack susceptibility in register-transfer level designs

Marco Bucci; R. Luzzi; Francesco Menichelli; Renato Menicocci; Mauro Olivieri; Alessandro Trifiletti

doi:10.1049/iet-ifs:20060112

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JOURNAL ARTICLE

Testing power-analysis attack susceptibility in register-transfer level designs

Marco Bucci R. Luzzi Francesco Menichelli Renato Menicocci Mauro Olivieri Alessandro Trifiletti

Year: 2007 Journal: IET Information Security Vol: 1 (3)Pages: 128-133 Publisher: Institution of Engineering and Technology

DOI: 10.1049/iet-ifs:20060112

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Abstract

The susceptibility of cryptographic devices to attacks based on power analysis can be both significantly and efficiently tested at early design steps. The results from a real case application show the advantages of the approach.

Keywords:

Power analysis Computer science Cryptography Linear feedback shift register Transfer (computing) Register-transfer level Shift register Computer security Logic gate Algorithm Logic synthesis Parallel computing Telecommunications

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Cryptographic Implementations and Security

Physical Sciences → Computer Science → Artificial Intelligence

Physical Unclonable Functions (PUFs) and Hardware Security

Physical Sciences → Computer Science → Hardware and Architecture

Chaos-based Image/Signal Encryption

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

Testing power-analysis attack susceptibility in register-transfer level designs

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