Reconfigurable randomized K-way graph partitioning

Abstract

In this paper, a randomized k-way graph partitioning algorithm is mapped onto reconfigurable hardware. The randomized algorithm relies on repetitive running of the same algorithm with different random number sequences to achieve the (near-)optimal solution. The run-time and hardware requirements of this reconfigurable solution per a random number sequence are O(|V|-K) cycles and O(|V|log|V|+|E|) gates and flip-flops, respectively. Performance is improved further at the expense of more hardware by running multiple copies of the partitioning algorithm with different random number sequences concurrently, and/or splitting a random sequence into subsequences and running them in parallel. Furthermore, in the context of this mapping, dynamic randomly configurable pattern-generation-based random number generation methods are introduced.