Low power high speed CMOS circuit design

Abstract

A novel low-power and high-speed master-salve Latches is proposed in this paper, thus the improvement of flip-flops and latches is one of the most critical tasks to enhance the system performance. The circuits are simulated on Tanner EDA tool with BSIM3V3 45nm CMOS technology for the calculation and comparison power delay product and both PDP and delay are better then other circuits. They are not only responsible for correct timing, functionality, and performance of the chips, but also their clocked devices consume a significant portion of the total active power. With increasing requirement for high-speed and low power, flip-flops with fewer transistors are preferred for their low power consumption and small area occupation.