A new scalable and reconfigurable architecture

Abstract

As optical link speeds get faster, demands for performance and embedded network services impose increasing flexibility demands. Internet routers must become more efficient and programmable. A new hardware architecture using a dynamic reconfigurable logic (DRL) circuit, along with its design methodology, is proposed. Our approach is to allocate all resources using the dynamic reconfigurable control switch (DRCS). The design space for scheduling the DRL for the networking application (router) is explored. Our proposal outperforms recent network processors since it has a better memory interface and because chained nodes of a thread can be executed at once. Our architecture offers an attractive alternative to expensive commercial solutions employing multiple content addressable memory (CAM) devices and application specific integrated circuits (ASICs). By providing high-performance at low per-ports costs, our architecture is a prime candidate for system-on-chip (SoC) solutions for next generation programmable router port processors.