Pipelined RISC Processor Design and FPGA Implementation

Li Gao; Hong Shan Zha

doi:10.4028/www.scientific.net/amm.336-338.1550

ScienceGate Book Chapters

JOURNAL ARTICLE

Pipelined RISC Processor Design and FPGA Implementation

Li Gao Hong Shan Zha

Year: 2013 Journal: Applied Mechanics and Materials Vol: 336-338 Pages: 1550-1553 Publisher: Trans Tech Publications

DOI: 10.4028/www.scientific.net/amm.336-338.1550

Get Full-Text PDF Get Analytical Report

Abstract

This paper presents a pipelined RISC architecture processor. Five-stage pipeline is used to enhance the performance. Test results show that: the design of processor able to accurately perform all instructions, reaching the functional requirements, and greatly improved performance. Finally, implement the pipelined RISC processor in FPGA.

Keywords:

Reduced instruction set computing Pipeline (software) Computer science Field-programmable gate array Processor design Embedded system Computer architecture Microarchitecture Instruction set Computer hardware Operating system

Metrics

Cited By

0.00

FWCI (Field Weighted Citation Impact)

Refs

0.09

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Citation History

Topics

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Pipelined RISC Processor Design and FPGA Implementation

Abstract

Metrics

Citation History

Topics

Related Documents

Design and FPGA Implementation of Five Stage Pipelined RISC -V Processor

VLSI Design Course with FPGA Implementation of Pipelined RISC-V Processor

Design and Implementation of 5-Stage Pipelined RISC-V Processor on FPGA

Low power pipelined 8-bit RISC processor design and implementation on FPGA

Pipelined 8-bit RISC processor design using Verilog HDL on FPGA