Lateral versus vertical gate-all-around FETs for beyond 7nm technologies

Abstract

Nominal L _G VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the L _G is possible and it results in an extra 27% in I _EFF in comparison to the nominal L _G case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.