Cache-Hierarchy Contention-Aware Scheduling in CMPs

Josué Feliu; Salvador Petit; Julio Sahuquillo; J. Duato

doi:10.1109/tpds.2013.61

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Cache-Hierarchy Contention-Aware Scheduling in CMPs

Josué Feliu Salvador Petit Julio Sahuquillo J. Duato

Year: 2013 Journal: IEEE Transactions on Parallel and Distributed Systems Vol: 25 (3)Pages: 581-590 Publisher: Institute of Electrical and Electronics Engineers

DOI: 10.1109/tpds.2013.61

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Abstract

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Keywords:

Computer science Cache Memory hierarchy Scheduling (production processes) Parallel computing Shared memory CPU cache Cache-only memory architecture Microprocessor Cache pollution Computer architecture Embedded system Cache algorithms Cache coloring

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Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Advanced Data Storage Technologies

Physical Sciences → Computer Science → Computer Networks and Communications

Cache-Hierarchy Contention-Aware Scheduling in CMPs

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