Electrical characterisation of Si‐SiO₂ structures

Abstract

Abstract The possibility of studying the Si‐SiO 2 structures by means of deep level transient spectroscopy (DLTS) has been presented. Contrary to the standard application of this technique, the temperature interval has to be reduced. In order to minimize the influence, and possible errors due to the capacitance base line shift and the Fermi level pinning, C‐V characterization at different temperatures is crucial prior the DLTS measurement. The interface traps related to the P b centers, distributed around 0.35 eV below the conduction band, have been observed (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)