RISC-based moving threads multicore architecture

Abstract

In this paper, we describe the architectural output of our `Moving threads realization study' (MOTH) project, which is a RISC-based multicore architecture framework. Each fraction of the memory can be accesses only via a certain core, via its cache memory. This approach leads to moving light-weight threads but at the same time provides strong memory coherences as no main memory location is replicated to several caches. We describe the overall multicore architecture, but special emphasis is put on describing the functionality of individual RISC-based core.