Lead‐free solder joint reliability estimation of flip chip package using FEM‐based sensitivity analysis

Abstract

Purpose Integration of Cu/low‐k interconnects into the next‐generation integrated circuit chips, particularly for devices below the 90 nm technology node, has proved necessary to meet the urgent requirements of reducing RC time delay and low power consumption. Accordingly, establishment of feasible and robust packaging technology solutions in relation to the structural design, as well as material selection of the packaging components, has become increasingly important. Moreover, the nature of low‐k materials and the use of lead‐free solder greatly increases the complications in terms of ensuring enhanced packaging level reliability. The foregoing urgent issue needs to be quickly resolved while developing various advanced packages. This paper aims to focus on the issues. Design/methodology/approach The prediction model, especially for the fatigue life of lead‐free solder joints, combined with virtual design of experiment with factorial analysis was used to obtain the sensitivity information of selecting geometry/material parameters in the proposed low‐k flip‐chip (FC) package. Moreover, a three‐dimensional non‐linear strip finite element model associated with the two levels of specified boundary condition of global‐local technique was adopted to shorten the time of numerical calculation, as well as to give a highly accurate solution. Findings The results of thermal cycling in experimental testing show good agreement with the simulated analysis. In addition, the sensitivity of analysis indicates that the type of underfill material has a significant effect on the lead‐free solder joint reliability. Originality/value A suitable combination of concerned designed factors is suggested in this research to enhance the reliability of low‐k FC packaging with Pb‐free solder joints.