On-chip high-Q inductor using wafer-level chip-scale package technology

Abstract

This paper characterizes of spiral inductor on silicon wafer using post-IC process. There are two critical factors to affect Quality factor of on-chip spiral inductor; one is a resistance of inductor, the other is substrate loss induced by eddy current. This paper demonstrated 10μm thick Cu film of inductor structure, to reduce the inductor resistance, and 10μm thick BCB dielectric material, which is a low-k material, separates inductor structure and silicon wafer to reduce the substrate loss. The Quality factor is over 45 at 2.4 GHz with inductance of 0.5 nH. In application, this technology can provide fully CMOS compatible and low temperature process.