<title>SIMD architecture for the Alopex neural network</title>

Abstract

The Alopex process is a biologically-influenced computational paradigm that uses a stochastic procedure to find the global optimum of linear and nonlinear functions. Unlike other neural networks, it is not a connectionist network with dense interconnections, and may be implemented in digital VLSI since the processing at the neuronal processing element (PE) level is simple and all PEs can be operated in synchrony. The Alopex algorithm uses the Boltzmann probability distribution function to generate probabilities of taking positive or negative steps away from its current position on the path toward the global optimal solution. Extensive simulations have verified the use of Alopex for solving a variety of problems. We present evaluation results of the effect of approximations, simplifications and level quantizations on the algorithm to yield simple, space-efficient and fast processing elements and other units. These modifications are necessary in order to implement Alopex in digital VLSI. Initial hardware modeling studies have involved a 4x4 array of neuronal PEs arranged for a Single-Instruction-Multiple-Data (SIMD) architecture. The model incorporates several digitally implementable solutions, such as a simpler Boltzmann probability density function (with a six-bit computation window), a binary annealing schedule, and a simpler cost function. Algorithmic simulations with an efficient image-processing system are described to support the feasibility and superiority of these modifications.