Electrical Characteristics of TiO₂/ZrSi_xO_y Stack Gate Dielectric for Metal-Oxide-Semiconductor Device Applications

Abstract

This short note describes a unique process for the preparation of high-quality titanium oxide (TiO 2 ) with zirconium silicate (ZrSi x O y ) as an interfacial layer for use in gate dielectric applications. Compared with conventional chemical oxide and oxynitride as an interfacial layer, titanium oxide (TiO 2 ) metal-oxide-semiconductor (MOS) capacitors with zirconium silicate (ZrSi x O y ) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm the achievement of the TiO 2 /ZrSi x O y stack structure by Auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The equivalent oxide thickness (EOT) and leakage current density at the gate bias 1 V below the flatband voltage ( V FB ) were 10.3 Å and 1 mA/cm 2 , respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.