A VLSI Design of High Speed Bit-level Viterbi Decoder

Abstract

When the authors implement high speed Viterbi decoder, the ACSU (add-compare-select unit) has been the main bottleneck. So, many studies have been advanced to solve the problem. The existing M-step look ahead technique processes ACSU by M-step stages and pursues high throughput by adopting new comparison algorithm through carry save number system. Also, minimized-method is a well-known high speed algorithm that removes nonlinear feedback from the ACSU by decoding both forward and backward directions. We first implemented the core-block of minimized method algorithm through bit-level basic processing element based on the look ahead technique. Next, the authors have reduced the area by applying code optimized array through retiming technique in backward direction which was used in the forward direction