Germanium v/s silicon Gate-all-around junctionless nanowire transistor

Abstract

In this paper, we have analyzed and evaluated Germanium and Silicon Gate-all-around junctionless transistor (GAA-JLT) transistors. We have compared the various analog and digital device performance parameters such as drain current I d , on-current I on , off-current I off , on-current to off current ratio I on /I off , drain induced barrier lower (DIBL), sub-threshold slope (SS), transconductance g m , transgeneration factor (TGF) and cut-off frequency f T are investigated using numerical device simulator 3-D ATLAS version 2.10.18.R. Extensive device simulations show Ge-GAA-JLT transistors has improvement in some dc device performance parameters as compared to Si-GAA-JLT transistors for both digital as well as analog applications. Ge-GAA-JLT shows the major improvement in terms of DIBL, lower threshold voltage and slight decrease in SS also. Hence, Ge-GAA-JLT is found to have improvement in device performance as compared with Si-GAA-JLT.