Hardware implementation design of analog sorting neural network

Abstract

Hardware implementation design in FPGA based reconfigurable computing architecture of analog neural network for parallel sorting is presented. The network has low computational and hardware implementation complexity. It is capable to process signals of any finite range, possesses signal order preserving property and does not require resetting and corresponding supervisory circuit that increases a speed of signal processing. A hardware implementation design is performed by using NI LabView Real-Time System. The hardware blocks are based on Altera FPGA Cyclone III and STM ARM32 Microcontroller Unit. Simulation results demonstrating the network performance are provided. According to simulation results, the network implemented in hardware demonstrates much higher speed of sorting comparatively to its software implementation.