A signal processing architecture for high throughput sensor processing

Abstract

DFT ESM EW FFT FIR FTR HTC HTP LSSD MS I MT I OCM SS I VHSIC VLSI Beamformer Complex Band S h i f t A S ing le M o n o l i t h i c S i l i c o n I n t e g r a t e d C i r c u i t Complex M u l t i p l y and Accumulate D i r e c t i o n a l Frequency Analys is and Recording D i g i t a l F o u r i e r Transform E l e c t r o n i c Support Measures E l e c t r o n i c Warfare Fast F o u r i e r Transform F i n i t e Impulse Response Funct ional Throughput Rate High Throughput C o n t r o l l e r High Throughput Processor Level S e n s i t i v e Scan Design Medium Scale I n t e g r a t i o n Moving Target I n d i c a t o r On-Chip Moni tor Small Scale I n t e g r a t i o n Very High Speed I n t e g r a t e d C i r c u i t Very Large Scale I n t e g r a t i o n Th is paper summarizes a s tudy performed t o d e r i v e sensor s i g n a l process ing requirements, and t o design a s i g n a l process ing a r c h i t e c t u r e capable o f per forming a l l o f t h e r e q u i r e d s i g n a l processing . General conclus ions a re t h a t t h e processing c lose t o t h e sensor r e q u i r e s very h igh throughput b u t i s w e l l s t ruc tu red , r e q u i r e s l i m i t e d f l e x i b i l i t y , and may be parameter programmed. A l l o f t h e systems a l s o r e q u i r e p rogramab le processors. The processor a r c h i t e c t u r e s vary apprec iab ly f rom system t o system. An a r c h i t e c t u r e w i t h h igh throughput f ron t -end processors fo l l owed by programmable processors meets a1 1 s i g n a l processing requirements and tends t o s i m p l i f y t h e s t ruc tu re . The f ron t -end processors b e n e f i t s i g n i f i c a n t l y from h ighthroughput VLSI ch ips designed f o r t h i s purpose. The Complex Mu1 t i p l y and Accumulate (CMAC) c h i p exempl i f i es such a design. I t i s capable o f per forming 100 m i l l i o n mu1 t i p 1 i e s per second, and i s designed t o e f f i c i e n t l y implement some o f t h e common s i g n a l process ing a lgor i thms. The a r c h i t e c t u r e a1 lows mu1 t i p l e CMACs t o be con f igu red i n t o an a r r a y capable o f over a b i l l i o n m u l t i p l i e s per second. Th is a r c h i t e c t u r e and c h i p a r e t o be i n i t i a l l y demonstrated aga ins t an a v i o n i c ant isubmarine war fa re requirement. I. Sensor Processing Requirements