A Parallel-Serial Decimal Multiplier Architecture

Abstract

Derived from a parallel multiplier, a parallel-serial decimal multiplier is proposed in which the multiplicand is assumed in parallel whereas the multiplier is in digit-serial form. A scheme for a parallel-serial decimal multiplier is presented, using BCD digits. The multiplicand is assumed in parallel, the multiplier in digit-serial form. The values of the Digit Products in the successive columns of the product array are added in binary and converted in decimal. Their decimal alignment generates a set of three or four serial decimal numbers whose sum is the product. The parallel-serial proposal substantially reduces complexity and it exploits overlapping update to speed up the pipeline. Evaluation on a basic implementation on FPGAs is compared against another embedded multiplier approach, showing that the proposed scheme achieves an increasing advantage as the input size increases.