JOURNAL ARTICLE

Spiking Neural Network Architecture

Paolo Montuschi

Year: 2015 Journal:   Computer Vol: 48 (10)Pages: 6-6   Publisher: IEEE Computer Society

Abstract

This installment of Computer's series highlighting the work published in IEEE Computer Society journals comes from IEEE Transactions on Computers. The first Web extra is a video in which Steve Furber introduces a paper, recently published in IEEE Transactions on Computers, that presents an overview of the architecture of the SpiNNaker massively parallel neurocomputer (https://youtu.be/EhPpxsK2Ia0). SpiNNaker was designed for brain-modeling applications, and will ultimately employ a million ARM processor cores to model up to a billion spiking neurons in biological real time. The second Web extra is a video in which the IEEE Computer Society presented its 2013 Computer Pioneer Award to Stephen B. Furber for pioneering work as a principal designer of the ARM 32-bit RISC microprocessor (https://youtu.be/x_H_6xG1TEs).

Keywords:
Computer science Microprocessor Architecture Massively parallel Principal (computer security) Reduced instruction set computing Computer architecture Operating system Software engineering Embedded system Computer hardware Instruction set

Metrics

3
Cited By
0.00
FWCI (Field Weighted Citation Impact)
2
Refs
0.03
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Neural Networks and Applications
Physical Sciences →  Computer Science →  Artificial Intelligence
Advanced Memory and Neural Computing
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Parallel Computing and Optimization Techniques
Physical Sciences →  Computer Science →  Hardware and Architecture
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